The News: Marvell launched its OCTEON 10 DPU designed to accelerate and process a broad spectrum of security, networking, and storage workloads required by 5G, cloud, carrier, and enterprise data center (DC) applications. With the increasing shift of workloads to the cloud, complex security requirements and the growing number of edge devices, the demand for data centric compute has accelerated.
By combining compute with accelerators, Marvell’s OCTEON 10 DPU (Data Processing Unit) seeks to offer a significant TCO (Total Cost of Ownership) advantage and features several industry innovations.
With the goal of delivering three times the performance and 50 percent lower power compared to previous generations of OCTEON, the new solution takes advantage of the 5nm process to incorporate Arm Neoverse N2 cores, as well as innovative inline artificial intelligence/machine learning (AI/ML) hardware acceleration, an integrated 1 terabit switch, and the incorporation of vector packet processing (VPP) hardware accelerators. Sampling of the new offering begins in H2 2021. Read the Marvell release here.
MWC 2021: Marvell OCTEON 10 DPU Launch Injects Innovation Boost to DPU Technology
Analyst Take: Marvell’s new OCTEON 10 DPU offering delivers the innovations needed to fulfill the data processing demands of fast-evolving DC and networking environments. The new product is ready to power the ecosystem-wide shift from application-centric compute to data-centric compute, particularly in meeting the AI, networking, security, video, and storage virtualization trend that is accelerating. Due to the ascent of data-centric computing, DPU technology has taken center stage to move, process, secure, and manage data, while in transit or rest, to make it available on an optimal basis for application.
From my perspective, Marvell has been at the forefront of DPU technology since its inception and its more recent popularization by silicon rival NVIDIA and others. Marvell’s prior generation OCTEON TX and OCTRON TX2 performed DPU duties in its nascent stage and now the new OCTEON 10 product takes DPU capabilities to the next level.
I see Marvell gaining significant differentiation in the DPU segment from the innovations embedded in the new OCTEON 10 offering. These distinctions include what I consider a merited claim of a first-to-market solution designed on the 5nm TSMC process that enables fanless designs and incorporates Arm Neoverse N2 cores (providing top industry SPECint – a computer benchmark benchmark for CPU integer processing power), unique inline DPU ML acceleration engine and VPP hardware accelerator capabilities, as well as support for an integrated 1 Tbps switch (16 x 50GE switch) and PCIe (Peripheral Component Interconnect express) 5.0 & DDR5 (Double Dare Rate 5) support. Taken together, these innovations enable Marvell to assert clearly differentiated performance per Watt across the OCTEON 10 suite, a major feature key to enabling DC users to meet their sustainability targets across their DC environments.
Marvell OCTEON 10 DPU: The Difference Makers
It is important to understand that the Marvell OCTEON 10 solution is also a platform proposition that combines the OCTEON DPU silicon with OCTEON DPU open software. The open software is key to assuring optimized stacks across the networking, storage, and security domains, scaling virtualization and container capabilities, as well as supporting standard APIs such as DPDK (Data Plane Development Kit), SPDK (Storage Performance Development Kit) , and VPP. Also, software is what enables the accelerator functions on the OCTEON 10 DPU.
The OCTEON 10 family’s support of an integrated ML engine that is placed directly in the data pipeline, with each ML tile containing private SRAM (Static Random-Access Memory), boosts DPU inferencing outcomes. This includes up to a hundredfold increase in performance over software-equivalent alternatives and strengthening top-priority use cases such as threat detection, context-aware service delivery, beamforming optimization, and predictive maintenance.
Through VPP hardware acceleration methods that act as a processing multiplier over existing 1 by 1 packet scheduling techniques embedded in existing scalar packet processing solutions, OCTEON 10 is now capable of delivering up to fivefold performance gains on both a per application and system-wide level. Moreover, I see built-in Arm Neoverse N2 benefits as enabling the OCTEON 10 DPU family to deliver up to a threefold improvement in single-threaded performance (allowing for the same software to run substantially faster), lower application latency with 1M L2 cache, up to a threefold latency reduction for connections to hardware accelerators, as well as assuring invaluable maximized performance per watt metrics.
The OCTEON 10 switch integration provides a 1T (Terabit) switch with 16 x 50 GE ports, with overall port support ranging from 1GE to 100GE. Key capabilities include 256bit MACsec support, network overlay for VxLAN/GRE/MPLS, network analytics, flow aware-processing, and line rate telemetry. Taken together these capabilities enable front haul/back haul/side haul applications across 5G implementations, agile edge switching, and enterprise Ethernet port fan out applications.
I see all these capabilities as providing the processing foundation for accelerating ecosystem-wide build of use cases such as service function chaining, 4G/5G RAN architecture expansion (for both disaggregated RAN and O-RAN/vRAN offload functions), cloud and DC DPU (i.e., 400G+ datapaths, 1K+ SPECint compute), and enterprise firewall/router application improvements in areas such as inline IPSec data plane acceleration.
Key Takeaways on the Marvell OCTEON 10 DPU Launch
I anticipate that the new Marvell OCTEON 10 DPU offering will gain rapid traction fulfilling the burgeoning security, networking, and storage workload demands of the DC, cloud, 5G, carrier, and enterprise realms as the sampling process unfolds in H2 2021.
In sum, I expect that Marvell’s OCTEON 10 DPU offers the enhanced processing capabilities essential to supporting and scaling rapidly growing parsing, classification, and inline IPSec applications. Key differentiators such as the incorporation of hardware accelerator advances make Marvell the frontrunner to meet the ecosystem-wide demand for inline ML and vector packet processing as well as Terabit switching capabilities needed to fulfill the stringent performance and low power requirements wherever DPUs are needed.
Disclosure: Futurum Research is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Other insights from Futurum Research:
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Marvell Takes Data Center Flash Storage to the Next Level with Bravera SC5 SSD Controller Debut
Marvell’s Q1 Earnings Results Are, Well, Pretty Marvelous, In Spite of Everything
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Author Information
Ron is an experienced, customer-focused research expert and analyst, with over 20 years of experience in the digital and IT transformation markets, working with businesses to drive consistent revenue and sales growth.
He is a recognized authority at tracking the evolution of and identifying the key disruptive trends within the service enablement ecosystem, including a wide range of topics across software and services, infrastructure, 5G communications, Internet of Things (IoT), Artificial Intelligence (AI), analytics, security, cloud computing, revenue management, and regulatory issues.
Prior to his work with The Futurum Group, Ron worked with GlobalData Technology creating syndicated and custom research across a wide variety of technical fields. His work with Current Analysis focused on the broadband and service provider infrastructure markets.
Ron holds a Master of Arts in Public Policy from University of Nevada — Las Vegas and a Bachelor of Arts in political science/government from William and Mary.
